0.35 2 2 BITS FLASH CELL BY EMPLOYING 0.35 STANDARD PROCESS AND METHOD FOR MANUFACTURING THE SAME

摘要

PURPOSE: A 2-bit flash memory cell using 0.35 micro meter standard processing and a method for manufacturing the same are provided to simplify process and to reduce cost by using a single gate oxidation. CONSTITUTION: A source(230) and a drain(232) are formed in a silicon substrate(200). A gate oxide layer(202) is formed on the silicon substrate. The first and second gates(210,212) are formed on the gate oxide layer. An ONO(SiO2/Si3N4/SiO2) structure is then formed by sequentially forming a lower oxide layer(222), a nitride layer(224) and an upper oxide layer(226) on the first and second gate. The ONO structure is connected with the first and second gate to control the coupling ratio, and the ONO structure is covered on the entire surface of the first and second gate to improve the retention characteristics of a flash cell.