首页> 外国专利> COMMUNICATION MODULE AND TRANSCEIVER INTEGRATED CIRCUIT TO REDUCE WIRE AREA COMMUNICATION MODULE AND TERMINALS TO BE INSTALLED AT TRANSCEIVER INTEGRATED CIRCUIT

COMMUNICATION MODULE AND TRANSCEIVER INTEGRATED CIRCUIT TO REDUCE WIRE AREA COMMUNICATION MODULE AND TERMINALS TO BE INSTALLED AT TRANSCEIVER INTEGRATED CIRCUIT

机译:通信模块和收发器集成电路,以减少电线区域通信模块和终端要安装在收发器集成电路中

摘要

PURPOSE: A communication module and a transceiver integrated circuit to reduce a wire area in a communication module and terminals to be installed at a transceiver integrated circuit are provided to reduce a wire area in a communication module by not using a dedicated terminal or wire for electric waves for each clock. CONSTITUTION: A bus(3) includes a data bus(3a) and a clock bus(3b). The data bus(3a) is used in common for either electric waves of data MDIO(Management Data Input/Output) conforming to a standard of an MDIO interface performed between a host controller IC(Integrated Circuit)(40) and a transceiver IC(1), or electric waves of data SDA conforming to a standard of I2C(Inter IC) performed between the transceiver IC(1) and a peripheral IC(2). The clock bus(3b) is used in common for either electric waves of clock MDC conforming to the MDIO interface performed between the host controller IC(40) and the transceiver IC(1), or electric waves of clock SCL conforming to a standard of I2C performed between the transceiver IC(1) and the peripheral IC(2).
机译:用途:通信模块和收发器集成电路,以减少通信模块中的导线面积,并提供要安装在收发器集成电路中的端子,以通过不使用电气专用端子或导线来减小通信模块中的导线面积每个时钟波浪。组成:总线(3)包括数据总线(3a)和时钟总线(3b)。数据总线(3a)共同用于数据MDIO(管理数据输入/输出)的电波,该电波符合在主机控制器IC(集成电路)(40)和收发器IC( 1),或者在收发器IC(1)和外围IC(2)之间执行的符合S2C(Inter IC)标准的数据SDA的电波。时钟总线(3b)共同用于符合在主机控制器IC(40)和收发器IC(1)之间执行的,与MDIO接口相一致的时钟MDC的电波,或与符合以下标准的时钟SCL的电波: I2C在收发器IC(1)和外围IC(2)之间执行。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号