VLSI ANALOG CHANNEL FOR MIXED-SIGNAL-VLSI TESTER

摘要

A mixed signal tester architecture and method is provided that minimizes the transfer of data, provides parallel data post-processing within analog channels, and allows for flexible synchronization. Each of the multiple analog channels captures a source digital signal processor (DSP), a digital source sequencer, a digital source instrument, an analog source instrument, an analog measurement instrument, a digital measurement instrument, a digital pin multiplexer, a digital measurement sequencer, a DSP addressable multi- A digital signal processor, and a DSP feedback path for communication between the source DSP and the acquisition DSP. Each analog channel can be placed in a feedback loop through either an analog instrument, a digital instrument, or an analog and digital instrument using the feedback path between the DSPs. The DUT response is processed in the channel, and the result is used to define parameters for a subsequent test cycle, and a signal corresponding to this parameter is generated and applied to the DUT. This loopback of the test cycle results within the analog channel to define the next test cycle increases the speed of the test process. The source DSP can synthesize the signal in real time and apply it to the DUT via an analog or digital source instrument and synthesize the source sequencer memory address (pointer to the waveform data stored in memory representing the waveform or waveform segment) And apply these signals to the DUT through an analog or digital source meter. The DUT response is written to capture memory in a channel that is directly addressable by the acquisition DSP to avoid transfer of data prior to processing and also increase the speed of the test process. The multi-bank capture memory controlled by the acquisition DSP allows data representing the DUT response to be written into one bank, while the previously recorded data in the other bank is processed. This interleaving of data acquisition and data processing allows simultaneous acquisition and processing, which additionally increases the speed of the test process.