The semiconductor memory element includes a storage cell array, and each cell has a transfer transistor having a gate electrode. A separate word line 32 interconnects the gate electrodes of each row of memory cells. The first conductive layer includes a stripe 38 and each stripe is on a separate row of memory cells and is connected to the gate electrodes and word lines of the memory cells in a separate odd numbered row of memory cells. The insulator surrounds the stripe of the first conductive layer. The second conductive layer separated from the stripe of the first conductor by the insulator comprises a stripe 39, each stripe of the second conductive layer being on a separate even numbered row of memory cells, Numbered gate electrodes and a word line. This arrangement reduces the parasitic delay caused by the word lines in the high density memory and increases the minimum pitch between stripes of any one level of the conductive layer.
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