INPUT BUFFER WITH DELAY REDUCTION PART OF SEMICONDUCTOR MEMORY DEVICE TO REDUCE DELAY OF EACH INVERTER NODE

摘要

PURPOSE: An input buffer of a semiconductor memory device is provided to reduce delay of each inverter node and to enable high speed operation by using a delay reduction part. CONSTITUTION: An input buffer comprises an inverter chain(10) composed of a plurality of inverters connected in series to delay an input signal, and a delay reduction part for reducing signal variation width. The delay reduction part is provided with a first signal variation width reduction part(20) for shifting a high level output signal to an upper limit of a trip point voltage level, and a second signal variation width reduction part(30) for shifting the high level output signal to a lower limit of the trip point voltage level.