Circuit arrangement for testing at least one of an integrated circuit output test signal, an arrangement of a test system for circuits can, use of the arrangement as well as a method for testing of at least one test signal

摘要

Circuit device (12) for testing at least one of an integrated circuit (11) output test signal (dqs) with– at least one test signal input (22, 24) for the signal input of the test signal (dqs);– at least one reference signal input (18, 20) for the signal input of a reference signal (pdy, pdz);– at least one comparator means (14, 16) which are coupled to a signal comparison of the test - with the reference signal (dqs; pdy, pdz) and for outputting an error signal is designed, if the signal comparison results in an error;– at least one error memory means (26, 28) for storing of the error signal; and– at least one with the error memory means (26, 28) is connected to the error signal output (38), characterized in that the test signal input (22, 24) with at least one first (14) and asecond comparator means (16) and connected at least a first (18) and a second (20) reference signal input is provided, whereby– the first comparator means (14) for outputting a first error signal is interpreted, when the voltage of the test signal (dqs) is greater than the..