Dynamic random-access memory circuit has memory bank divided into regions in turn divided into segments provided with master datalines for each segment diverging from region bus

摘要

The memory circuit has at least one memory bank (10) divided into several regions, the memory cell columns in each region divided into segments, with a respective bus (26a,26b) for each region and a bundle of master datalines (ML) for each segment, coupled to a line network for addressing the individual memory cells. The region buses are cyclically coupled to a common data port (22) via a multiplexer (23), a control device (30) for the read and write operations allowing the beginning of a read phase to overlap the end of a write phase. A data latch (28) is coupled to each master dataline for holding the applied data group, a separation switch (27) controlled by the control device allowing the master datalines to be separated from the region bus. An Independent claim for an operating method for a random-access memory circuit is also included.