Clock signal generation circuit using phase-locked loop for generation of HF clock signal from analogue input signal

摘要

The circuit has a phase comparator (8) providing an output value (dphi) dependent on the phase difference between a supplied signal (13) and a reference phase, received by a regulator (5) for a controlled oscillator (6) providing the HF clock signal (OUT). An analogue input signal (IN) is sampled via an A/D converter (1) at a sampling frequency (fT) obtained from the HF clock signal, the digital sample values fed to the phase comparator.