首页> 外国专利> speicherarchitektur for flexible leseverwaltung, especially for non-volatile memory with rauschunempfindlichkeitsmerkmalen, anlageleistungsanpassung and with optimised flow

speicherarchitektur for flexible leseverwaltung, especially for non-volatile memory with rauschunempfindlichkeitsmerkmalen, anlageleistungsanpassung and with optimised flow

机译:存储器架构可实现灵活的读取管理,特别是用于具有抗噪功能,系统性能调整和优化流程的非易失性存储器

摘要

A memory architecture for flexible reading management, particularly for non-volatile memories, comprising: at least one memory matrix (1); at least one sense amplifier (7) for capturing the data from the at least one memory matrix (1); at least one output buffer (8) for providing the read data in output, connected to the sense amplifier by means of an internal bus; and at least one row decoder (3) for selecting the word lines of the memory matrix; characterized in that it furthermore comprises: -- a memory read address transition detection circuit (25), adapted to produce an address transition signal (ATD); -- a circuit (13) for enabling/disabling the read circuits; -- a circuit (11) for enabling the reading process, adapted to enable reading only after the minimum functionality levels of the memory cells involved in the reading operation and of all the connected read circuits have been reached; -- a network (12) for equalizing and correlating the reading with respect to the characteristics of the devices, the signal propagations, and the conductivity of the memory cells, the propagations being detected by a propagation reproduction circuit; -- a reading cycle end circuit (14), adapted to determine the end of the reading process by deactivating the row decoder following the capture of the read data item in the sense amplifier; and -- a circuit (15) for the synchronized and time-limited loading of the data in the at least one output buffer (8), the output buffer having a memory structure and being normally disconnected from the internal circuits, the enabling of the reading process being performed in close correlation with the intrinsic characteristics of the read circuits and of the memory cells. IMAGE
机译:一种用于灵活的读取管理,特别是用于非易失性存储器的存储器架构,包括:至少一个存储器矩阵(1);至少一个读出放大器(7),用于从至少一个存储矩阵(1)捕获数据;至少一个输出缓冲器(8),用于通过内部总线连接到读出放大器,以提供输出中的读取数据;至少一个行解码器(3),用于选择存储矩阵的字线;其特征还在于:-存储器读取地址转换检测电路(25),适于产生地址转换信号(ATD); -用于启用/禁用读取电路的电路(13); -用于启动读取过程的电路(11),适用于仅在达到读取操作所涉及的存储单元和所有连接的读取电路的最低功能级别后才能进行读取; -一个网络(12),用于根据设备的特性,信号传播和存储单元的电导率来均衡读数并使之相关,该传播由传播再现电路检测; -读取周期结束电路(14),适于通过在读出放大器中读取数据项的捕获之后使行解码器去激活来确定读取过程的结束; -电路(15),用于在至少一个输出缓冲器(8)中同步且有时间限制地加载数据,所述输出缓冲器具有存储器结构,并且通常与内部电路断开连接,使得能够读取过程与读取电路和存储单元的固有特性紧密相关。 <图像>

著录项

  • 公开/公告号DE69631242D1

    专利类型

  • 公开/公告日2004-02-05

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS S.R.L. AGRATE BRIANZA;

    申请/专利号DE19966031242T

  • 发明设计人 PASCUCCI LUIGI;

    申请日1996-04-29

  • 分类号G11C7/00;

  • 国家 DE

  • 入库时间 2022-08-21 22:40:57

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