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A method for controlling a cache - memory in a multiprocessor system and a multiprocessor system

机译:用于控制多处理器系统中的高速缓冲存储器的方法和多处理器系统

摘要

PROBLEM TO BE SOLVED: To attain the dynamic switching of a cache control protocol without touching any structural body indicating the attribute of an area being the destination of access such as a segment describer or a page describer. ;SOLUTION: Plural processors 1 and 2 equipped with each cache memory 11 and 12 constitute a multiprocessor system sharing a main storage 3 through a system bus 4. Each processor 1 and 2 is provided with module detecting means 13 and 23 for detecting the execution of modules for performing access to a shared memory area on the main storage 3. Memory access to be performed in the modules detected by the module detecting means 13 and 23 is controlled by a store-through system cache control protocol for updating the main storage 3 at the same time as the update of the cache memories 11 and 12, and memory access to be performed in the other modules is controlled by a store-in system cache control protocol not for updating the main storage 3 at the time of the update of the cache memories 11 and 21.;COPYRIGHT: (C)2000,JPO
机译:要解决的问题:在不触及指示访问目标的区域属性的任何结构体(例如段描述器或页面描述器)的情况下,实现高速缓存控制协议的动态切换。 ;解决方案:配备有每个高速缓存存储器11和12的复数个处理器1和2构成了一个多处理器系统,该多处理器系统通过系统总线4共享一个主存储器3。每个处理器1和2都配备有模块检测装置13和23,用于检测处理器的执行。用于访问主存储器3上的共享存储器区域的模块。由模块检测装置13和23检测的模块中要执行的存储器访问由用于更新主存储器3的直通系统高速缓存控制协议控制。在与高速缓冲存储器11和12的更新相同的时间,在其他模块中执行的存储器访问由存储系统高速缓存控制协议控制,该协议不用于在更新存储单元时更新主存储器3。快取记忆体11和21;版权:(C)2000,JPO

著录项

  • 公开/公告号DE69909400T2

    专利类型

  • 公开/公告日2004-04-15

    原文格式PDF

  • 申请/专利权人 NEC CORP. TOKIO/TOKYO JP;

    申请/专利号DE1999609400T

  • 发明设计人 AINO SHIGEYUKI MINATO-KU TOKYO JP;

    申请日0000-00-00

  • 分类号G06F12/08;

  • 国家 DE

  • 入库时间 2022-08-21 22:40:10

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