METHOD OF CONTROLLING CACHE MEMORY IN MULTIPROCESSOR SYSTEM AND THE MULTIPROCESSOR SYSTEM

摘要

Cache control protocols can be switched duringrunning without changing an architecture for a segmentdescriptor or page descriptor for indicating an attributeof an area to be accessed. A plurality of processorseach including a cache memory constitute a multiprocessorsystem which shares a main memory via a system bus. Eachprocessor has module detecting means for detectingexecution of a module which accesses a shared memory areaon the main memory, by comparing the virtual space numberand the instruction segment number concerning theaccessing module with those numbers concerning thesoftware modules preset which may access the sharedmemory area. Memory access executed in a module detectedby the module detecting means is controlled in a cachecontrol protocol of a store-through scheme which updatesa main memory simultaneously with update of a cachememory. Memory access executed in other modules iscontrolled in a cache control protocol of a store-inscheme which does not update a main memory at update of acache memory.