Memory cell which is electrically programmable by degrading at least locally the gate oxide layer of a MOS transistor so to obtain a current variation in reading operation

摘要

The memory cell or point memory which is of electrically programmable read-only type comprises a MOS transistor with the gate oxide layer (14) and the gate (G) which is electrically connected. In programming operation the gate oxide layer (14) is degraded at least locally at point Z so to obtain in the reading operations a variation of current (Id) delivered by the transistor. The MOS transistor is a transistor with thin gate oxide layer (GO1), whose thickness is substantially equal to 2.5 nm. The gate oxide layer (14) is degraded as a function of used programming voltages. The degradation of the gate oxide layer is implemented in the full length of transistor channel (12), or in the vicinity of at least one electrode, source (S) and drain (D), in particular the drain electrode. A method (claimed) for programming the memory cell (claimed) consists of applying the programming voltages to the transistor electrodes which cause an irreversible degradation of the gate oxide layer of the transistor so that the read current (Id) is varied. In the course of programming the gate voltage is equal to at least 1.2 V, the voltage between the source and the drain is equal to about 3 V, and the bulk voltage is negative and qual to about -1 V. A method (claimed) for reading the memory cell consists of applying between the drain and the source a voltage in the range from 0.1 V to 1.2 V. An integrated circuit (claimed) comprises a central part with MOS transistors having the thin gate oxide layer (GO1) and a peripheral part with MOS transistors having a thicker gate oxide layer (GO2). The central part comprises a flat memory comprising memory cells with the MOS transistors having the thin gate oxide layer. In the write operation the programming voltages are applied to cause the degradation of the gate oxide layer of the selected transistor. A higher programming voltage is applied either to the drain or to the source of the memory cell so to cause degradations in the respective zones of the gate oxide layer. Each memory cell is also associated with another transistor allowing an adjustment of the source voltage of non-selected transistors. The thickness of the thicker gate oxide layer is substantially equal to 7 nm. The lower and the higher supply voltages are about 1.2 V and 3.3 V, respectively.