Finite field processor reconfigurable for varying sizes of field.

摘要

A finite field processor has input registers for storing the operands, an arithmetic unit with sub-units to preform arithmetic operations on the operands and an output register to store the result. The input registers may have multiple operand registers, the arithmetic unit has the same number of sub-units and the control unit can produce the same number of control signals to configure the field sizes of the multiple sub-units. The arithmetic sub-units can be operated independently and concurrently. Also the arithmetic sub-units can co-operate in response to control signals to operate on operands that have field sizes greater than the dynamic range of any one arithmetic sub-unit. The sub-units can be arranged to operate on different sizes of field at the same time. The operands could be global and represent the coefficients of a polynomial. The processor could be a Domain processor, particularity a Galois field processor. Also disclosed is a reconfigurable processor with a plurality of arithmetic units each with a plurality of sub-units, each sub-unit having dynamic ranges that are defined by predetermined field sizes.