A processor array with redundancy in which functionality is removed from a row containing a faulty processing element

摘要

A processor array, or method, comprising a plurality of processor elements AExx (20, in figure 1, which may be only memory devices), buses 41, 42 (and 41-44, 32, 36 in figure 1) and switches SWxx wherein the processor elements AExx form rows and columns and are interconnected by buses, switches being placed at the bus intersections; such that in the event that a processing element AExx is found to be faulty no functionality is allocated to any processing element in its row 45. Preferably a redundant row of processor elements is used to functionally replace a faulty row, the bus structure being designed to accommodate this replacement. The replacement can either be performed by switching from a faulty row to a redundant row or by switching a first (faulty) rows functionality to a second adjacent row then switching this second row with a further row, and so on, until the redundant row is used. Also disclosed is a processor array in which all rows of processing elements are the same and pairs of horizontal buses carrying data in opposite directions are provided between the rows and two pairs of vertical buses carrying data in opposite directions are provided between some of the colunms. The invention is used to allow useful products to be created despite point defects in wafers (figure 4) and also to allow operational faults to be bypassed.