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Clock induced supply noise reduction method and apparatus for a latch based circuit

机译:用于基于锁存器的电路的时钟感应电源降噪方法和装置

摘要

A method and a apparatus for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.
机译:已经开发了用于减少与基于锁存器的电路的时钟信号相关的噪声的方法和设备。该方法包括在时钟周期的预定时间存储电荷,并且还在时钟周期的预定时间释放存储的电荷。与锁存器的操作同步,电荷由时钟信号释放到系统的电网上。

著录项

  • 公开/公告号GB2393340A

    专利类型

  • 公开/公告日2004-03-24

    原文格式PDF

  • 申请/专利权人 * SUN MICROSYSTEMS INC.;

    申请/专利号GB20040001936

  • 发明设计人 CLAUDE R * GAUTHIER;BRIAN W * AMICK;

    申请日2002-07-29

  • 分类号H03K19/003;H03K3/01;

  • 国家 GB

  • 入库时间 2022-08-21 22:38:07

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