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Stretching, shortening, and/or removing a clock cycle
Stretching, shortening, and/or removing a clock cycle
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机译:延长,缩短和/或删除时钟周期
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摘要
A method and apparatus for stretching and/or shortening a clock cycle uses a multiplexor stage, in which a multiplexor switches between a normal clock signal and a delayed clock signal. Further, a method and apparatus for generating a plurality of stretched and/or shortened clock cycles uses a multiplexor state in which a multiplexor successively switches between a normal clock signal and a plurality of delayed clock signals. Further, a method and apparatus for removing a clock cycle uses a multiplexor stage, in which a multiplexor switches between either a normal clock signal or a delayed clock signal and a grounded signal.
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