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MULTIPLEX VOLTAGE OUTPUT CIRCUIT AND LOGIC GATE CIRCUIT FOR MULTIPLEX VOLTAGE OUTPUT CIRCUIT

机译:用于多路电压输出电路的多路电压输出电路和逻辑门电路

摘要

PPROBLEM TO BE SOLVED: To provide a driving circuit suited to low power drive for a portable display and the like by removing a through current, which is probably generated in a driving circuit, at selecting time of output voltages at a multiplex voltage output stage as in the driving circuit of a flat display. PSOLUTION: Two signals, which have the same timing and with which only one phase is reversed, are entered to two logical gates to obtain each logical gate output signal. In the multiplex voltage output circuit, one of multiplex output voltages is selectively generated by driving each gate of two corresponding MOS transistors, which function as switching for the power source voltage, based on the two output signal. The sizes of PMOS and NMOS, which constitute the logical gate, are made different with each other, and in the multiplex voltage output circuit, the two gate outputs are not put under the same condition of low L or high H, by advancing or delaying a raise edge and/or a decline of the output signal and the like. PCOPYRIGHT: (C)2006,JPO&NCIPI
机译:

要解决的问题:通过在多路电压下选择输出电压时去除可能在驱动电路中产生的直通电流,从而提供一种适用于便携式显示器等低功率驱动的驱动电路输出级,如平板显示器的驱动电路。

解决方案:具有相同时序且仅将一个相位反转的两个信号输入两个逻辑门以获得每个逻辑门输出信号。在多路复用电压输出电路中,通过基于两个输出信号驱动两个对应的MOS晶体管的每个栅极来选择性地生成多路复用输出电压之一,该两个相应的MOS晶体管用作电源电压的切换。构成逻辑门的PMOS和NMOS的大小彼此不同,并且在多路电压输出电路中,通过提前或延迟,两个门输出不会处于低L或高H的相同条件下输出信号的上升沿和/或下降等。

版权:(C)2006,JPO&NCIPI

著录项

  • 公开/公告号JP2005295491A

    专利类型

  • 公开/公告日2005-10-20

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC;

    申请/专利号JP20040195050

  • 发明设计人 LIM DAE-HO;

    申请日2004-06-30

  • 分类号H03K17/16;G09G3/20;G09G3/36;H03K17/00;H03K17/687;H03K19/0948;

  • 国家 JP

  • 入库时间 2022-08-21 22:37:03

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