首页> 外国专利> BEHAVIORAL SYNTHESIS SYSTEM, BEHAVIORAL SYNTHESIS METHOD, CONTROL PROGRAM, READABLE STORAGE MEDIUM, MANUFACTURING METHOD OF LOGIC CIRCUIT, AND LOGIC CIRCUIT

BEHAVIORAL SYNTHESIS SYSTEM, BEHAVIORAL SYNTHESIS METHOD, CONTROL PROGRAM, READABLE STORAGE MEDIUM, MANUFACTURING METHOD OF LOGIC CIRCUIT, AND LOGIC CIRCUIT

机译:行为合成系统,行为合成方法,控制程序,可读存储介质,逻辑电路的制造方法和逻辑电路

摘要

PPROBLEM TO BE SOLVED: To pipeline loop processing in a CDFG (control data flow graph) with a minimum increase in area in a behavioral synthesis for synthesizing hardware from a behavior description. PSOLUTION: When the loop processing is pipelined, a loop control part 31 for outputting a control signal for making each node included in the loop processing perform at least a non-loop processing of the loop processing and the non-loop processing is provided within a loop processing part 30 of a control data flow graph showing that each node is divided for every pipelining stage, and the processing of each pipelining stage is executed in parallel every time the loop processing to be carried out in a plurality of times to generate the CDFG. PCOPYRIGHT: (C)2005,JPO&NCIPI
机译:

要解决的问题:在CDFG(控制数据流图)中进行流水线循环处理,在行为合成中以最小的面积增加以从行为描述中合成硬件。

解决方案:当对循环处理进行流水线处理时,用于输出控制信号的循环控制部31使该循环处理中包括的每个节点至少执行该循环处理的非循环处理。设置在控制数据流图的循环处理部分30内的控制数据流图表示每个流水线阶段都划分了每个节点,并且每次要进行多次循环处理时,并行执行每个流水线阶段的处理,生成CDFG。

版权:(C)2005,JPO&NCIPI

著录项

  • 公开/公告号JP2004326463A

    专利类型

  • 公开/公告日2004-11-18

    原文格式PDF

  • 申请/专利权人 SHARP CORP;

    申请/专利号JP20030120600

  • 发明设计人 OKADA KAZUHISA;

    申请日2003-04-24

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 22:34:21

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