AUTOMATIC LAYOUT APPARATUS, LAYOUT MODEL GENERATION APPARATUS, LAYOUT MODEL VERIFICATION APPARATUS, AND LAYOUT MODEL

摘要

PPROBLEM TO BE SOLVED: To provide an automatic layout apparatus in which all design rule violations due to wiring between cells are avoided without reducing the integration of a semiconductor device and sharply increasing wiring processing time. PSOLUTION: The automatic layout apparatus generates the layout of a semiconductor apparatus by arranging and wiring cell layout constituted so as to have specific functions. The automatic layout apparatus arranges and wires the cell layouts on the basis of a layout model, and the layout model is provided with the graphic information of the cell layouts which is necessary for wiring between cell layouts and the information on a wiring prohibited area 21 in which wiring is regarded as a design rule violation. PCOPYRIGHT: (C)2005,JPO&NCIPI