首页> 外国专利> STANDARD CELL LAYOUT, STANDARD CELL LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS DESIGN METHOD

STANDARD CELL LAYOUT, STANDARD CELL LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS DESIGN METHOD

机译:标准单元布局,标准单元库,半导体集成电路及其设计方法

摘要

PROBLEM TO BE SOLVED: To provide a standard cell layout capable of suppressing the leak current without changing the existing processes, a standard cell library thereof, a semiconductor integrated circuit using the standard cell layout and its design method.;SOLUTION: This standard cell layout, which is used to design a semiconductor integrated circuit and is provided with one or more MOS transistors as logical cells, is included in a standard cell library and is provided with a domain for arranging an extended poly between a gate poly 11 constituting a gate electrode of the above-mentioned MOS transistor(s)and an adjacent contact 12.;COPYRIGHT: (C)2005,JPO&NCIPI
机译:要解决的问题:提供一种能够在不改变现有工艺的情况下抑制泄漏电流的标准单元布局,其标准单元库,使用该标准单元布局的半导体集成电路及其设计方法。用于设计半导体集成电路并具有一个或多个MOS晶体管作为逻辑单元的晶体管,包括在标准单元库中,并且具有用于在构成栅电极的栅极多晶硅11之间布置扩展多晶硅的域MOS晶体管及其相邻触点12的结构;版权所有:(C)2005,JPO&NCIPI

著录项

  • 公开/公告号JP2005236210A

    专利类型

  • 公开/公告日2005-09-02

    原文格式PDF

  • 申请/专利权人 RICOH CO LTD;

    申请/专利号JP20040046631

  • 发明设计人 YOSHIOKA KEIICHI;

    申请日2004-02-23

  • 分类号H01L21/82;H01L21/822;H01L27/04;

  • 国家 JP

  • 入库时间 2022-08-21 22:32:40

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