Efficient handling due to the positive and negative of the overflow of hardware that occurs as a result of an arithmetic operation

摘要

A computer system provides handling of positive and negative overflow. A first arithmetic operation is performed on a first n-bit unsigned binary operand and a second n-bit signed binary operand to produce an n-bit unsigned binary result. Overflow detection logic circuitry (300,310,320,330) within the arithmetic logic unit (26) detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic (340,341,350,351) replaces the output of the two's complement adder (60,61,65,66,69) with a value of 2n-1. When there is a negative overflow, the saturation logic (340,341,350,351) replaces the output of the two's complement adder (60,61,65,66,69) with a value of 0. In the same embodiment, a second arithmetic operation is performed on two n-bit signed binary operands to produce an n-bit signed binary result. The arithmetic operation is for example an addition or subtraction performed by a two's complement adder (60,61,65,66,69). Overflow detection logic circuitry (300,310,320,330) within the arithmetic logic unit (26) detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic (340,341,350,351) replaces the output of the two's complement adder (60,61,65,66,69) with a value of 2n-1-1. When there is a negative overflow, the saturation logic (340,341,350,351) replaces the output of the two's complement adder (60,61,65,66,69) with a value of -2n-1. IMAGE