Failure in a combinational logic circuit propagation path estimation system and method, and program

摘要

PROBLEM TO BE SOLVED: To estimate a fault propagation route in a fault propagation route estimation system for estimating a fault spot inside a logic circuit by tracking the fault propagation route from a fault terminal by repeating temporary decision of a logic and implication operation.;SOLUTION: This system is equipped with a temporary decision limiting determination means 28 for providing an upper limit of the temporary decision level for showing the number of times of the temporary decision of the logic state, and switching temporary determination of the logic state to simplified retrieval of the fault propagation route, when the number of times of the temporary decision of the logic state exceeds the upper limit of the temporary decision level, and a first fault propagation route simplified retrieval means 30 for extracting fan-in cone by tracing a net list of a combinational logic circuit in the input direction from an indefinite gate having a gate output signal in the fault state and having a signal wire whose logic state is an undefined state in input-output signal wires, and registering a signal wire whose logic state is not defined included in the fan-in cone as the fault propagation route.;COPYRIGHT: (C)2003,JPO