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Automatic floor-planning method capable of shortening floor-plan processing time
Automatic floor-planning method capable of shortening floor-plan processing time
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机译:可缩短平面图处理时间的自动平面图制作方法
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摘要
An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.
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