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Method and device for handling write access conflicts in interleaving for high throughput turbo-decoding
Method and device for handling write access conflicts in interleaving for high throughput turbo-decoding
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机译:用于高吞吐量turbo解码的交织中的写访问冲突的处理方法和装置
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摘要
A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.
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