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Instruction cache and method for reducing memory conflicts
Instruction cache and method for reducing memory conflicts
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机译:指令缓存和减少存储器冲突的方法
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摘要
Read/write conflicts in an instruction cache memory (11) are reduced by configuring the memory as two even and odd array sub-blocks (12,13) and adding an input buffer (10) between the memory (11) and an update (16). Contentions between a memory read and a memory write are minimised by the buffer (10) shifting the update sequence with respect to the read sequence. The invention can adapt itself for use in digital signal processing systems with different external memory behaviour as far as latency and burst capability is concerned.
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