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Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay
Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay
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机译:在时间延迟到期后,以一系列计算单元的形式读取所选寄存器,从而形成处理流水线
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摘要
A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.
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