Systems and methods for implementing a rate converting, low-latency, low-power block interleaver

摘要

A rate-converting, low-latency, low power interleaver architecture is implemented using block read-write methods. The memory architecture is such that it allows multiple input bits to be written into memory simultaneously. In some embodiments, the number of simultaneous bits written into memory corresponds to an error encoding rate, such that an encoder and interleaver can operate within the same clock domain, regardless of the code rate. The memory architecture also allows an entire row of interleaved data to be read out in one clock cycle.