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Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations
Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations
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机译:在多个间隔的设备位置的总线中点处设置读写时钟信号之间的预定相位关系的存储系统
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摘要
A clock system for a data bus, e.g., a memory bus system, provides a write data (WCLK) clock signal in one direction on a bus and a data read (RCLK) clock signal in an opposite direction on the bus. A predetermined phase relationship between said WCLK and RCLK clock signals is set at a predetermined location on the data bus to ensure that all memory subsystems connected to the bus receive the WCLK and RCLK signals with appropriate timing to ensure proper operation of the memory subsystems.
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