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Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs
Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port RAMs
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机译:通过自动测试码型生成生成的测试序列,适用于具有嵌入式多端口RAM的电路
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摘要
A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.
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