首页> 外国专利> Maximally digitized fractional-N frequency synthesizer and modulator with maximal fractional spurs removing

Maximally digitized fractional-N frequency synthesizer and modulator with maximal fractional spurs removing

机译:最大数字化的小数N分频合成器和调制器,最大去除了小数杂散

摘要

A fractional-N frequency synthesizer using the first order Delta-Sigma frequency discriminator which is composed of only a dual modulus frequency divider and a D flip-flop is used to replace the function of phase detector is disclosed. The invented structure is characterized by generating the feedback error signal indirectly from the output bit stream of said discriminator in such a way that the quantization noise contained in the bit stream is maximally canceled by comparing it with another bit stream generated by an accumulator digitally performing the first order Delta-Sigma modulation to the required fractional number, so that there is almost no discrete fractional spurs in the output spectrum of the synthesizer. Most other circuit of the synthesizer could be formed digitally so that high integration level and low noise performance could be achieved. Narrow or wideband phase or frequency modulation could also be conveniently added digitally with good accuracy.
机译:公开了使用仅由双模分频器和D触发器组成的使用一阶Δ-Σ分频器的分数N频率合成器来代替相位检测器的功能。本发明的结构的特征在于,以如下方式从所述鉴别器的输出比特流间接地产生反馈误差信号,即,通过将其与数字化累加器的累加器生成的另一比特流进行比较,来最大程度地消除该比特流中包含的量化噪声。一阶Delta-Sigma调制到所需的分数,因此合成器的输出频谱中几乎没有离散的分数杂散。合成器的大多数其他电路可以数字方式形成,从而可以实现高集成度和低噪声性能。窄带或宽带相位或频率调制也可以方便地以良好的精度以数字方式添加。

著录项

  • 公开/公告号US6946915B2

    专利类型

  • 公开/公告日2005-09-20

    原文格式PDF

  • 申请/专利权人 XIAOPIN ZHANG;

    申请/专利号US20030656762

  • 发明设计人 XIAOPIN ZHANG;

    申请日2003-09-08

  • 分类号H03L7/085;H03L7/10;H03L7/16;H03C3/00;H04L27/12;

  • 国家 US

  • 入库时间 2022-08-21 22:20:08

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