首页> 外国专利> Low threading dislocation density relaxed mismatched epilayers without high temperature growth

Low threading dislocation density relaxed mismatched epilayers without high temperature growth

机译:低穿线位错密度可缓解不匹配的外延层,而无需高温生长

摘要

A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C. above the deposition temperature of the second semiconductor layer.
机译:一种半导体结构及其处理方法,包括:衬底;晶格失配的第一层沉积在衬底上并在高于沉积温度的100°C以上的温度下退火;以及第二层,沉积在具有更大的第二层上与第一半导体层相比,晶格与基板不匹配。在另一个实施例中,提供了一种在半导体衬底上的半导体梯度组成层结构及其处理方法,该结构包括半导体衬底,第一半导体层,该第一半导体层具有沉积在衬底上并在更高温度下退火的一系列晶格不匹配的半导体层。在高于沉积温度100°C的温度下,沉积在第一半导体层上的第二半导体层与衬底的晶格失配大于第一半导体层,并在高于沉积温度100°C的温度下退火。第二半导体层。

著录项

  • 公开/公告号US6864115B2

    专利类型

  • 公开/公告日2005-03-08

    原文格式PDF

  • 申请/专利权人 EUGENE A. FITZGERALD;

    申请/专利号US20020268025

  • 发明设计人 EUGENE A. FITZGERALD;

    申请日2002-10-09

  • 分类号H01L21/00;

  • 国家 US

  • 入库时间 2022-08-21 22:19:15

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