The PLL with symbols rate carrier deleted oriented decision with discriminator and phase programmable extrapolation phase rate of chip.

摘要

"PLL rate with symbols of a deleted oriented to the decision phase discriminator and phase programmable extrapolation of the rate of chip.A method and apparatus are described for phase locked loop.A typical apparatus includes a demodulator that receives an error signal from a phase comparator at a rate of chip and provides an update of the phase error for a period of symbol provenieNTE of the error signal of phase in which the rate of chip is greater than the symbol rate.A phase discriminator produces an output error of phase to the symbol rate from the phase error update based on a type of modulation signal.A loop filter produces one or more parameters to estimate phase to a symbol rate from the phase error output and a numerically controlled oscillator (NCO) extrapolates a reference ofPhase at a rate of chip from the one or more parameters to estimate phase to a symbol rate.The comparator produces the error signal to the demodulator phase based on the phase reference and an incoming signal.