DECISION DIRECTED SUPPRESSED CARRIER SYMBOL-RATE PLL WITH PROGRAMMABLE PHASE DISCRIMINATOR AND CHIP-RATE PHASE EXTRAPOLATION

摘要

The phase locked loop system and method are presented. A typical device receives the phase error signal with a higher chip rate and symbol rate from the comparator comprises a demodulator for providing a phase error update over a symbol period from the phase error signal. The phase discriminator produces a phase error output at the symbol rate from the phase error update based upon a signal modulation type. The loop filter output for one or more phase estimate parameters at a symbol rate from the phase error output and a numerically controlled oscillator (NCO) extrapolates a phase reference at a chip rate from the one or more phase estimate parameters at a symbol rate. The comparator produces the phase error signal to the demodulator based upon the phase reference and an incoming signal.