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EXPLOITING SHORTEST PATH FOR IMPROVED NETWORK CLOCK DISTRIBUTION

机译:探索改善网络时钟分配的最短路径

摘要

Apparatus and methods are provided for exploiting the existence of a shortest path between a source (102) and a destination (104) device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector (302) and a low pass filter (304) of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.
机译:提供了一种装置和方法,用于通过识别最短路径并使用优先采用最短路径的信号来优先利用源(102)和目的地(104)设备之间最短路径的存在,而不是延迟传输或延迟图像。相同的信号,从而改善信号分配。本发明提供了一种在锁相环的相敏检测器(302)和低通滤波器(304)之间的处理器,用于主要从采用最短路径的信号中选择和驱动PLL。

著录项

  • 公开/公告号WO2004051874A3

    专利类型

  • 公开/公告日2005-01-27

    原文格式PDF

  • 申请/专利权人 CIRRUS LOGIC INC.;

    申请/专利号WO2003US38821

  • 发明设计人 GROSS KEVIN PAUL;

    申请日2003-11-25

  • 分类号H03D3/24;

  • 国家 WO

  • 入库时间 2022-08-21 22:12:42

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