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Exploiting shortest path for improved network clock distribution

机译:利用最短路径改善网络时钟分配

摘要

Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.
机译:提供了一种装置和方法,用于通过识别最短路径并使用已采用最短路径的信号优先于同一信号的延迟传输或延迟图像来利用源设备和目的地设备之间最短路径的存在,从而改善信号分配。本发明提供了一种在相敏检测器和锁相环的低通滤波器之间的处理器,主要用于从采用最短路径的信号中选择和驱动PLL。

著录项

  • 公开/公告号US6973152B2

    专利类型

  • 公开/公告日2005-12-06

    原文格式PDF

  • 申请/专利权人 KEVIN PAUL GROSS;

    申请/专利号US20020310554

  • 发明设计人 KEVIN PAUL GROSS;

    申请日2002-12-04

  • 分类号H03D3/24;

  • 国家 US

  • 入库时间 2022-08-21 21:40:35

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