Method of analysis of the quality of contacts and vias in multi-level metallisation fabrication processes of semiconductor devices, and corresponding test chip architecture

摘要

A test chip has been conceived to perform all the measurements needed to evaluate the performances of interconnects (in particular, to measure the statistical failure distribution, the electromigration, and the leakage current), and an algorithm has been developed to detect the via failure at any of the available n metal layers. The test chip consists basically of a ROM memory array. The vias to be measured are realized in the columns of the array. Vias (or contact) failures are detected by forcing a predetermined current through both an array column and a reference column. The required failure analysis is attained by comparing the resulting voltage drops.