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Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture
Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture
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机译:半导体器件多金属制造工艺中触点和通孔的质量分析,方法和测试芯片架构
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摘要
A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.
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