首页> 外国专利> MULTIPLIER-DIVIDER CIRCUIT FOR A PFC CONTROLLER

MULTIPLIER-DIVIDER CIRCUIT FOR A PFC CONTROLLER

机译:PFC控制器的乘法器-除法电路

摘要

The present invention introduces an integrated analog multiplier-divider circuit. The multiplier-divider block according to the present invention is ideal for use in the power factor correction (PFC) controllers of many switch-mode power supplies. The analog multiplier-divider according to the present invention is built from CMOS devices. Because of this, it has many advantages over prior-art multiplier-dividers. One important advantage is that the die-size and the cost can be reduced. Another important advantage of the multiplier-divider according to the present invention is substantially reduced temperature dependence.
机译:本发明介绍了一种集成的模拟乘法器-除法器电路。根据本发明的乘法器-除法器模块非常适合用于许多开关电源的功率因数校正(PFC)控制器。根据本发明的模拟乘法器-除法器由CMOS器件构成。因此,与现有技术的乘法器-除法器相比,它具有许多优点。一个重要的优点是可以减小芯片尺寸和成本。根据本发明的乘法器-除法器的另一个重要优点是大大降低了温度依赖性。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号