Test structures for on-chip real-time reliability testing

摘要

Described is a system with three on chip monitoring test structures. If any of the three test structures indicates an end of life failure, a bit will be set indicating that the IC is near failure and should be replaced. This is done prior to actual device failure and will eliminate down time of the system where this IC is used. The first test structure monitors hot carrier degradation and is comprised of two ring oscillators. One is subjected to hot carrier effects (degrading ring oscillator) and the other is not subjected to hot carrier effects (non-degrading ring oscillator). Initially, both ring oscillators will each have fixed frequencies, but as the device ages, hot carrier effects degrade the degrading ring counter. Using the non-degrading ring oscillator, the degradation can be quantified and flag a failure. The second test structure monitors TDDB degradation. A plurality of N parallel connected capacitors have a stress voltage applied to them such that the time to failure of the first capacitor is the same time to failure experienced by 0.1 percentile of gates under normal usage. Breakdown of a capacitor is observed by a drop in the resistance of the structure and is used to trigger a bit indicating a TDDB end of life signal. The third test structure monitors electromigration degradation. M minimum width metal lines are connected in parallel. A current is applied to them such that the time to failure of all metal lines is the same as the time to failure experienced by 0.1 percentile of minimum width metal lines under normal usage. Breakdown of a metal line is observed by an increase in the resistance of the structure and is used to trigger a bit indicating an electromigration end of life signal. 0.1 percentile is given as an example and can be varied depending upon the users definition of device lifetime.