Dual FPGA using dual damascene process and its manufacturing method

摘要

PURPOSE: A dual field programmable gate array using a dual damascene fabrication process and a fabricating method thereof are provided to enhance the productivity by increasing the number of chips within the same wafer size. CONSTITUTION: The first IMD layer(21) and the first etch-stop layer(22) are formed on a metal layer(20). The second IMD layer(23) is formed thereon. A trench is pattered by performing a CMP process. A trench etch process is performed. A via pattern is formed on a trench-etched region. A via etch process is performed on a predetermined region for forming a via pattern. An amorphous silicon layer is developed and patterned on a via-etched region. A via barrier metal(27) is deposited on the via-etched region and the patterned region. A sputtering process and an etch-back process are performed on the deposited region. The amorphous silicon layer is developed and patterned on the deposited region and the etched region(28). A metal is deposited and etched on the patterned region(29).