首页> 外国专利> METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE TO PREVENT GENERATION OF TRAP SITE OF LOWER PART OF TRENCH

METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE TO PREVENT GENERATION OF TRAP SITE OF LOWER PART OF TRENCH

机译:形成半导体器件隔离层以防止沟槽下陷部位产生的方法

摘要

PURPOSE: A method of forming an isolation layer of a semiconductor device is provided to prevent the generation of a trap site by removing a liner nitride layer from a lower part of a trench. CONSTITUTION: A trench is formed in a silicon substrate(200) by using a pad nitride layer as a hard mask. A liner oxide layer(240) and a liner nitride layer(250) are sequentially formed within the trench. The liner nitride layer is removed from a lower part of the trench and a round oxide layer is formed on the lower part of the trench by oxidation. The round oxide layer is removed therefrom in order to form the lower part of the trench having a round shape.
机译:目的:提供一种形成半导体器件的隔离层的方法,以通过从沟槽的下部去除衬里氮化物层来防止陷阱位点的产生。组成:使用氮化硅垫作为硬掩模在硅衬底(200)中形成沟槽。在沟槽内依次形成衬里氧化物层(240)和衬里氮化物层(250)。从沟槽的下部去除衬里氮化物层,并且通过氧化在沟槽的下部上形成圆形氧化物层。从其上去除圆形氧化物层,以形成具有圆形形状的沟槽的下部。

著录项

  • 公开/公告号KR20050003294A

    专利类型

  • 公开/公告日2005-01-10

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20030044014

  • 发明设计人 LEE EUN SUK;PARK HYO SIK;

    申请日2003-06-30

  • 分类号H01L21/76;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:03

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