首页> 外国专利> RECESS TYPE TRANSISTOR AND FABRICATING METHOD THEREOF FOR OVERCOMING RESTRICTION SUCH AS CRITICAL DIMENSION OF GATE STACK LARGER THAN OPEN CRITICAL DIMENSION OF TRENCH BY OVERLAPPING GATE STACK ON GROWN SILICON

RECESS TYPE TRANSISTOR AND FABRICATING METHOD THEREOF FOR OVERCOMING RESTRICTION SUCH AS CRITICAL DIMENSION OF GATE STACK LARGER THAN OPEN CRITICAL DIMENSION OF TRENCH BY OVERLAPPING GATE STACK ON GROWN SILICON

机译:克服栅栏临界尺寸而使开孔临界尺寸大于开孔临界尺寸的硅衬底上的栅型晶体管及其制造方法

摘要

PURPOSE: A recess type transistor and a fabricating method thereof are provided to overcome a restriction such as a critical dimension of a gate stack larger than an open critical dimension of a trench by overlapping a gate stack on grown silicon. CONSTITUTION: A semiconductor substrate(52) has an active region defined by an isolation layer. One or more trench(60) is formed on the active region. A grown silicon layer(64) is formed along an inner face of the trench. A gate insulating layer is formed on the grown silicon layer within the trench and on the active region. A gate electrode(68) is formed on the gate insulating layer. A top side is larger than a bottom side in the gate electrode. An impurity region(78) is formed on the active region corresponding to both sides of the gate electrode.
机译:目的:提供一种凹陷型晶体管及其制造方法,以通过将栅极堆叠在生长的硅上而克服诸如栅极堆叠的临界尺寸大于沟槽的开口临界尺寸之类的限制。构成:半导体衬底(52)具有由隔离层限定的有源区。在有源区上形成一个或多个沟槽(60)。沿着沟槽的内表面形成生长的硅层(64)。在沟槽内的生长的硅层上和有源区上形成栅极绝缘层。在栅绝缘层上形成栅电极(68)。栅电极的顶侧大于底侧。在与栅电极的两侧相对应的有源区上形成杂质区(78)。

著录项

  • 公开/公告号KR20050004352A

    专利类型

  • 公开/公告日2005-01-12

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20030044502

  • 发明设计人 KIM JI YOUNG;

    申请日2003-07-02

  • 分类号H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:03

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