首页> 外国专利> ULTRA LARGE SCALE INTEGRATION SEMICONDUCTOR DEVICE FORMED ON SOI AND FABRICATING METHOD THEREOF TO DROP OPERATIONAL VOLTAGE APPLIED TO DRAIN

ULTRA LARGE SCALE INTEGRATION SEMICONDUCTOR DEVICE FORMED ON SOI AND FABRICATING METHOD THEREOF TO DROP OPERATIONAL VOLTAGE APPLIED TO DRAIN

机译:SOI制的超大规模集成半导体器件及其制造方法,以降低流失在排水中的工作电压

摘要

PURPOSE: An ultra large scale integration semiconductor device formed on an SOI and a fabricating method thereof are provided to drop an operational voltage applied to a drain by reducing the amount of NM ions in an ion implantation process. CONSTITUTION: A gate oxide layer(115) is formed on an active region. A gate poly(108) is formed on the gate oxide layer. A first lightly-doped drain spacer(140) is formed on a lateral part of the gate oxide layer and the gate poly on the active region. A second lightly-doped drain spacer(142) is formed on the first lightly-doped drain spacer. A salicide layer(130) is formed on a peripheral part of the active region and on the gate poly. A plurality of metal connections(132,134,136) are formed on the salicide layer.
机译:目的:提供一种在SOI上形成的超大规模集成半导体器件及其制造方法,以通过减少离子注入工艺中的NM离子量来降低施加到漏极的工作电压。组成:在有源区上形成栅氧化层(115)。在栅极氧化物层上形成栅极多晶硅(108)。在有源区上的栅极氧化物层和栅极多晶硅的侧面部分上形成第一轻掺杂漏极隔离物(140)。在第一轻掺杂漏极隔离物上形成第二轻掺杂漏极隔离物142。在有源区的外围部分和栅极多晶硅上形成自对准硅化物层(130)。在自对准硅化物层上形成多个金属连接(132,134,136)。

著录项

  • 公开/公告号KR20050011578A

    专利类型

  • 公开/公告日2005-01-29

    原文格式PDF

  • 申请/专利权人 MAGNACHIP SEMICONDUCTOR LTD.;

    申请/专利号KR20030050737

  • 发明设计人 KIM YONG KUK;

    申请日2003-07-23

  • 分类号H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:55

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