首页> 外国专利> METHOD FOR FABRICATING SEMICONDUCTOR DEVICE TO GUARANTEE RELIABILITY OF ELECTROMIGRATION AND STRESS MIGRATION OF COPPER INTERCONNECTION

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE TO GUARANTEE RELIABILITY OF ELECTROMIGRATION AND STRESS MIGRATION OF COPPER INTERCONNECTION

机译:制造半导体器件以保证铜互连的电渗析和应力迁移的可靠性的方法

摘要

PURPOSE: A method for fabricating a semiconductor device is provided to guarantee reliability of electromigration and stress migration of a copper interconnection by improving an etch profile of a dual damascene pattern. CONSTITUTION: A multilayered insulation layer for a dual damascene pattern is deposited on a semiconductor substrate(10) having a lower metal interconnection. A via hole(33) is formed in the multilayered insulation layer. A photoresist layer is left only in the via hole. A trench(139) is formed in the multilayered insulation layer. After the photoresist layer in the via hole is removed, the lower metal interconnection is exposed. An upper metal interconnection is formed in the via hole and the trench to be electrically connected to the lower metal interconnection. While the upper surface of the photoresist layer remaining in the via hole is lower than the bottom surface of the trench, the trench is formed so that an etch profile of a round type is formed in the bottom surface of the trench adjacent to the via hole.
机译:目的:提供一种用于制造半导体器件的方法,以通过改善双镶嵌图案的蚀刻轮廓来确保铜互连的电迁移和应力迁移的可靠性。构成:用于双镶嵌图案的多层绝缘层沉积在具有较低金属互连的半导体衬底(10)上。在多层绝缘层中形成通孔(33)。光致抗蚀剂层仅留在通孔中。在多层绝缘层中形成沟槽(139)。在去除通孔中的光致抗蚀剂层之后,露出下部金属互连。上金属互连形成在通孔和沟槽中,以电连接到下金属互连。当残留在通孔中的光致抗蚀剂层的上表面低于沟槽的底表面时,形成沟槽,使得在与通孔相邻的沟槽的底表面中形成圆形的蚀刻轮廓。 。

著录项

  • 公开/公告号KR20050020481A

    专利类型

  • 公开/公告日2005-03-04

    原文格式PDF

  • 申请/专利权人 DONGBUANAM SEMICONDUCTOR INC.;

    申请/专利号KR20030058481

  • 发明设计人 KEUM DONG YEAL;

    申请日2003-08-23

  • 分类号H01L21/3205;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:46

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