首页> 外国专利> APPARATUS AND METHOD FOR CODING/DECODING BLOCK LDPC CODES IN A MOBILE COMMUNICATION SYSTEM FOR MAXIMIZING ERROR CORRECTION PERFORMANCE AND MINIMIZING CODING COMPLEXITY

APPARATUS AND METHOD FOR CODING/DECODING BLOCK LDPC CODES IN A MOBILE COMMUNICATION SYSTEM FOR MAXIMIZING ERROR CORRECTION PERFORMANCE AND MINIMIZING CODING COMPLEXITY

机译:在移动通信系统中编码/解码块LDPC码以最大化误差校正性能和最小化编码复杂度的装置和方法

摘要

PURPOSE: An apparatus and a method for coding/decoding block LDPC codes in a mobile communication system are provided to improve system performance by maximizing error correction performance and minimizing coding complexity by using an effective parity check matrix. CONSTITUTION: A variable node decoder(2011) connects variable nodes corresponding to respective weight of plural columns. The columns constitute a parity check matrix according to a predetermined control. The variable node decoder detects probability values of received signals. A first adder(2015) subtracts a pre-decoded signal from an output of the variable node decoder. A deinterleaver(2017) deinterleaves the output of the first adder corresponding to the parity check matrix. A check node decoder(2027) connects variable nodes corresponding to respective weight of plural columns. The check node decoder detects probability values of the output of the deinterleaver. A second adder(2025) subtracts an output of the deinterleaver from an output of the second adder. An interleaver(2019) interleaves the output of the second adder corresponding to the parity check matrix and outputs the result to the variable node decoder and the first adder. A controller(2021) generates the parity check matrix and controls overall components.
机译:目的:提供一种用于在移动通信系统中对块LDPC码进行编码/解码的设备和方法,以通过使用有效的奇偶校验矩阵最大化纠错性能并最小化编码复杂度来提高系统性能。构成:可变节点解码器(2011)连接对应于多列各自权重的可变节点。这些列构成根据预定控制的奇偶校验矩阵。可变节点解码器检测接收信号的概率值。第一加法器(2015)从可变节点解码器的输出中减去预解码的信号。 Deinterleaver(2017)对与奇偶校验矩阵相对应的第一个加法器的输出进行解交织。校验节点解码器(2027)连接对应于多列的各个权重的变量节点。校验节点解码器检测解交织器的输出的概率值。第二加法器(2025)从第二加法器的输出中减去解交织器的输出。交织器(2019)对与奇偶校验矩阵相对应的第二加法器的输出进行交织,并将结果输出至可变节点解码器和第一加法器。控制器(2021)生成奇偶校验矩阵并控制整个组件。

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