PURPOSE: A structure of a test device group of a planar capacitor is provided to improve reliability and an electrical characteristic by examining the influence that the size of an impurity ion implantation region of a planar capacitor has an effect upon a semiconductor device. CONSTITUTION: A test device group of a planar capacitor is composed of at least two test devices. A transistor is formed on a semiconductor substrate(11), composed of a gate oxide layer(13G), a wordline(14G), a drain(15D) and a source(15S). A bitline(17) is connected to the drain. A planar capacitor is formed on the semiconductor substrate at the source, composed of a dielectric layer(13C) and a top plate electrode(14C). An impurity ion implantation region(100-1 - 100-n) is formed in the surface of the semiconductor substrate under the top plate electrode. An interlayer dielectric(16) is formed on the semiconductor substrate including the wordline and the top plate electrode.
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