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METHOD OF ERROR DETECTION AND RESTORATION IN MULTI-POINT TYPE HDLC BUS

机译:多点式HDLC总线中的错误检测与恢复方法

摘要

The present invention relates to H. D. elssi (HDLC) bus error detection and recovery methods of a specific block that is abnormal to occupy the bus in use. Error detection and recovery methods of a multi-point method HDLC bus according to the present invention, in one of the master board (master board) and a plurality of slave boards (slave board) error detection and recovery methods of a multi-point method HDLC bus connecting each slave board is a first step of the transition when the abnormal operation by checking that the account for the bus over a predetermined time by using a BUSY (bus occupied) signal the BUSY signal and the CTS signal to terminate the bus occupation is forced to a High state .; To recover the abnormal operation of the bus a second step in which the slave boards by the HDLC FPGA logic generates a reset (reset), and reset the interrupt for the resource driver (FCC or SCC); If the abnormal operation of the bus to continue the slave board to create a REQ signal and a BUSY signal to prevent the bus occupation is forced to a High state, to set the error bit to 1 in that it comprises a third step of transmitting to the master board It characterized.
机译:本发明涉及在使用中占用总线异常的特定块的H.D.elssi(HDLC)总线错误检测和恢复方法。根据本发明的多点方法HDLC总线的错误检测和恢复方法,在主板(主板)和多个从属板(从板)之一中,多点方法的错误检测和恢复方法连接每个从属板的HDLC总线是过渡的第一步,当异常操作通过使用BUSY(总线占用)信号,BUSY信号和CTS信号来检查总线帐户是否在预定时间内检查总线帐户以终止总线占用时被迫进入高状态。为了恢复总线的异常运行,第二步,HDLC FPGA逻辑的从板产生一个复位(复位),并复位资源驱动器的中断(FCC或SCC);如果总线的异常操作继续使从板产生REQ信号和BUSY信号以防止总线被占用,则将其设置为高状态,则将错误位设置为1,因为这包括向主板它的特点。

著录项

  • 公开/公告号KR20050060766A

    专利类型

  • 公开/公告日2005-06-22

    原文格式PDF

  • 申请/专利权人 LG ELECTRONICS INC.;

    申请/专利号KR20030092484

  • 发明设计人 CHOI YOUNG LIM;

    申请日2003-12-17

  • 分类号H04L12/24;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:07

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