Integrated circuit having memory cell array configuration capable of operating data reading and data writing simultaneously

摘要

An integrated circuit having a memory cell array structure, read operation and write operation are performed at the same time is disclosed. The integrated circuit according to the present invention, a plurality of memory blocks provided in the integrated circuit where the write address and read address for, and the input and output ports separated from one period of the clock signal input at the same time, each of a plurality of sub-block of memory, the memory written in the blocks of the data memory blocks and the write address or in response to the read address the memory block the data and the data memory block corresponding to or reading out and a tag memory control unit, said sub memory blocks the write address and the read address input at the same time shall not access the same sub-block of memory even if the same at the same time. The data memory block, if having the same size as the one sub-block of memory is characterized in that which may have a number of the sub-block of memory and another column (column) with different number of rows (row). Each address of the tag memory control unit sub If the memory block is {2} ^ {N} dog, includes a N + 1 data bits, the N + 1 data bits of the N bits indicate the data memory address, the remaining one bit is characterized in that it represents the effective determination information. An integrated circuit having a memory cell array configuration in accordance with the present invention has the advantage of being able to shorten the period of the clock signal, thereby performing the read operation and the write operation at the same time during one period of the clock signal.