High speed 8bit/10bit encoder/decoder by reduction of logic group

摘要

The present invention relates to a high-speed 8-bit / 10-bit encoder / decoder according to the logic stage reduction for data communication.; Logic-stage high-speed 8-bit / 10-bit encoder by reducing the present invention are 5 bits to calculate the 0 and 1 of the 6-bit output data number is a balance of the input data of 5 bits by using a two-stage logic synthesis techniques / 6-bit encoding function block unit, a 3-bit / 4-bit encoding function block unit for the number of 0's and 1's in the input data of 3 bits by using a two-stage logic synthesis techniques calculate the output data of four bits are balanced, disparity a generation has a technical feature in yirueojim portion disparity calculation block outputs.; Therefore, high-speed 8-bit / 10-bit encoder / decoder by reducing the logic of the present invention only has focused on the 8-bit / 10-bit encoder / decoder used for transmission of data in a data communication on the speed rather than the size of the structure of the logic gate the second stage uses the logic synthesis technique, it is effective to make a minimal number of steps in the logic gate level, data processing is possible to ensure a more reliable and fast operation is made.