UNIVERSAL noise immunity DECODER nonsystematic convolutional codes

摘要

1.universal u043fu043eu043cu0435u0445u043eu0443u0441u0442u043eu0439u0447u0438u0432u044bu0439 decoder u043du0435u0441u0438u0441u0442u0435u043cu0430u0442u0438u0447u0435u0441u043au0438u0445 u0441u0432u0435u0440u0442u043eu0447u043du044bu0445 codes containing the switch, the evaluator of the metrics and consistently about u0446u0435u0441u0441u043eu0440, device u043fu0430u043cu00a0u0442u0438 ways and the evaluation of the quality of the channel, as well as the system u0432u0435u0442u0432u0435u0432u043eu0439 u0443u0441u0442u0440u0430u043du0435u043du0438u00a0 synchronization and disambiguation, which first exit u0434u043au043bu044eu0447u0435u043d to the switch, with the first, the second,the third and fourth outputs are connected respectively to the u0432u044bu0447u0438u0441u043bu0438u0442u0435u043bu00a0 metrics of the first, second, third and fourth u0432u0445u043eu0434u0430u043c processor, u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 what it introduced the device inserts u0441u0442u0438u0440u0430u043du0438u0439 ", the first and second entrances which are connected respectively with the first and second outputs of the switch, the with the second and third inputs device to evaluate the quality of the channel, and the firstthe second, third and fourth outputs, respectively, with the first, second, third and fourth inputs u0432u044bu0447u0438u0441u043bu0438u0442u0435u043bu00a0 metrics of branches, the second processor u043fu043eu0434u043au043bu044e exit chen to the entrance of u0432u0435u0442u0432u0435u0432u043eu0439 u0443u0441u0442u0440u0430u043du0435u043du0438u00a0 synchronization and disambiguation, the second outlet which is connected to the third gate device inserts "u0441u0442u0438u0440u0430u043du0438u0439".;2. decoder for p.1, u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 what device u043fu0430u043cu00a0u0442u0438 ways implemented as two parallel routes, each of which contains has the operational art u0430u043cu00a0u0442u044c ram, the switchboard, the register latch, a multiplexer, which is connected to the second outlet door switch, consistently the third multiplexer.the first and second entrances which are connected to the exits of registers, latches the first and second adjustment, the majority element and a third operational u043fu0430u043cu00a0u0442u044c ram, as well as u0443u0441u0442u0440 u043eu0439u0441u0442u0432u043e u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0, first and second outputs of which are connected respectively to the first and second u0432u0445u043eu0434u0430u043c operational u043fu0430u043cu00a0u0442u0438 first tract, third and fourth number from the first and second u0432u0445u043eu0434u0430u043c operational u043fu0430u043cu00a0u0442u0438 second tractu043fu00a0u0442u044bu0439 exit u0432u0445u043eu0434u0430u043c add drop multiplexers to the first and second tract, the sixth way to the second the third u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, seventh and eighth exits - the of course for the second and third u0432u0445u043eu0434u0430u043c third operational u043fu0430u043cu00a0u0442u0438, with third place operational u043fu0430u043cu00a0u0442u0438 first and second tract are connected to the first gate ol u043eu0446u0435u0441u0441u043eu0440u0430,and a third operational u043fu0430u043cu00a0u0442u0438 - to the first door device to evaluate the quality of the channel.